integrated circuit systems, inc. general description features ICS9148-46 block diagram pentium/pro tm system clock chip 9148-46 rev e 4/20/99 pin configuration 28 pin ssop pentium is a trademark on intel corporation. ? generates system clocks for cpu, pci, 14.314 mhz, 48 and 24mhz. ? supports single or dual processor systems ? skew from cpu (earlier) to pci clock 1 to 4ns ? separate 2.5v and 3.3v supply pins ? 2.5v outputs: cpu ? 3.3v outputs: pci, ref ? no power supply sequence requirements ? 28 pin ssop ? spread sectrum operation optional for pll1 ? cpu frequencies to 100mhz are supported. the ICS9148-46 is part of a reduced pin count two-chip clock solution for designs using an intel bx style chipset. companion sdram buffers are ics9179-03, and -12. there are two plls, with the first pll capable of spread spectrum operation. spread spectrum typically reduces system emi by 8-10db. the second pll provides support for usb (48mhz) and 24mhz requirements. cpu frequencies up to 100mhz are supported. the i 2 c interface allows stop clock programming, frequency selection, and spread spectrum operation to be programmed. clock outputs include two cpu (2.5v or 3.3v), five pci (3.3v), two ref (3.3v), one 48mhz, and one selectable 48_24mhz. ground groups gnd = ground source core, cpuclk (0:1) gnd1 = ref(0:1), x1, x2 gnd2 = pciclk_f, pciclk (0:5) gnd3=48mhz, 24/48mhz power groups vdd = supply for pll core vdd1 = ref(0:1), x1, x2 vdd2 = pciclk_f, pciclk (0:3) vdd3 = 48mhz, 24/48mhz vddl = cpuclk (0:1) ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.
2 ICS9148-46 pin descriptions r e b m u n n i pe m a n n i pe p y tn o i t p i r c s e d 11 d n gr w p. 2 x , 1 x , ) 1 : 0 ( f e r r o f d n u o r g 21 xn i f p 3 3 l a n r e t n i s a h , t u p n i l a t s y r c z h m 8 1 3 . 4 1 n i _ l a t x 2 x m o r f r o t s i s e r k c a b d e e f d n a p a c d a o l 32 xt u of p 3 3 p a c d a o l l a n r e t n i s a h , t u p t u o l a t s y r c t u o _ l a t x 42 d n gr w ps t u p t u o i c p r o f d n u o r g 5f _ k l c i c pt u o# p o t s _ i c p y b d e t c e f f a t o n . t u p t u o i c p g n i n n u r e e r f 0 1 , 9 , 7 , 6) 3 : 0 ( k l c i c pt u ov 3 . 3 e l b i t a p m o c l t t . s t u p t u o k c o l c i c p 82 d d vr w pv 3 . 3 y l l a n i m o n , s t u p t u o k l c i c p r o f r e w o p 1 13 d d vr w pz h m 8 4 r o f r e o p 2 1z h m 8 4t u oz h m 8 4 @ t u p t u o k l c d e x i f 3 1z h m 8 4 _ 4 2t u o , p u r e w o p t a 1 = 7 2 n i p f i z h m 4 2 ; t u p t u o k l c d e x i f . p u r e w o p t a 0 = 7 2 n i p f i z h m 8 4 4 13 d n gr w pz h m 8 4 r o f d n u o r g 5 1# 6 . 6 6 / 0 0 1 l e sn i z h m 6 . 6 6 r o z h m 0 0 1 g n i l b a n e r o f n i p t c e l e s s u o n o r h c n y s s y a w l a i c p ( z h m 6 . 6 6 = l , z h m 0 0 1 = h ) z h m 3 . 3 3 6 1k l c sn ii r o f t u p n i k c o l c 2 t u p n i c 7 1a t a d sn ii r o f t u p n i a t a d 2 t u p n i c 8 1# d pn i s e l b a s i d ) w o l ( e v i t c a n e v i r d n e h w t u p n i s u o n o r h c n y s a d e c a l p e r a s t u p t u o l l a . y l r a e o c v s p o t s , s k c o l c l a n r e t n i . e l c y c t n e r u c e h t f o d n e e h t t a e t a t s w o l a n i 9 1# p o t s _ u p cn i s p o t s ) w o l ( e v i t c a n e v i r d n e h w t u p n i s u o n o r h c n y s a . e t a t s w o l a n i ) 1 : 0 ( k l c u p c 0 2# p o t s _ i c pn i s p o t s ) w o l ( e v i t c a n e v i r d n e h w t u p n i s u o n o r h c n y s a . d e t c e f f a t o n s i f _ k l c i c p . e t a t s w o l a n i ) 3 : 0 ( k l c i c p 1 2d n gr w pe r o c e h t d n a ) 1 : 0 ( k l c u p c r o f d n u o r g 2 2d d vr w pe r o c l l p r o f r e w o p 4 2 , 3 2) 0 : 1 ( k l c u p ct u ov 5 . 2 y l l a n i m o n s t u p t u o k c o l c t s o h d n a u p c 5 2l d d vr w pv 5 . 2 y l l a n i m o n , s t u p t u o u p c r o f r e w o p 6 21 f e rt u ot u p t u o k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 7 21 d d vr w p. s t u p t u o f e r r o f r e w o p 8 2 0 f e rt u ot u p t u o k c o l c z h m 8 1 3 . 4 1 # 8 4 l e sn i. z h m 8 4 s i 3 1 n i p , w o l n e h w . p u r e w o p t a t u p n i d e h c t a l
3 ICS9148-46 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support intel piix4 "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. for more information, contact ics for an i 2 c programming application note. how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address d2 (h) ? ics clock will acknowledge ? controller (host) sends a dummy command code ? ics clock will acknowledge ? controller (host) sends a dummy byte count ? ics clock will acknowledge ? controller (host) starts sending first byte (byte 0) through byte 5 ? ics clock will acknowledge each byte one at a time . ? controller (host) sends a stop bit how to read: ? controller (host) will send start bit. ? controler (host) sends the read address d3 (h) ? ics clock will acknowledge ? ics clock will send the byte count ? controller (host) acknowledges ? ics clock sends first byte (byte 0) through byte 6 ? controller (host) will need to acknowledge each byte ? controller (host) will send a stop bit notes: controller (host) ics (slave/receiver) start bit address d2 (h) ac k dummy command code ac k dummy byte count ack byte 0 ac k byte 1 ac k byte 2 ack byte 3 ac k byte 4 ac k byte 5 ack byte 6 ac k stop bit how to write: controller (host) ics (slave/receiver) start bit address d3 (h) ac k byte coun t ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack byte 6 ack stop bit how to read:
4 ICS9148-46 note: pwd = power-up default byte 3: functionality & frequency select & spread slect register notes: 1 = enabled; 0 = disabled, outputs held low byte 4: notes: 1 = enabled; 0 = disabled, outputs held low t i b# n i pe m a n n i pd w p n o i t p i r c s e d 0 = e u l a v t i b1 = e u l a v t i b 7- - - ) d e v r e s e r () d e v r e s e r ( 6- - - ) d e v r e s e r () d e v r e s e r ( 5- - - ) d e v r e s e r () d e v r e s e r ( 4- - - ) d e v r e s e r () d e v r e s e r ( 3- - - ) d e v r e s e r () d e v r e s e r ( 23 21 k l c u p c1 d e l b a s i d ) w o l ( d e l b a n e 1- - 0 ) d e v r e s e r () d e v r e s e r ( 04 20 k l c u p c1 ) d e l b a s i d ( ) w o l ( d e l b a n e byte 5: notes: 1 = enabled; 0 = disabled, outputs held low t i b# n i pe m a n n i pd w p n o i t p i r c s e d 0 = e u l a v t i b1 = e u l a v t i b 75 f _ k l c i c p1 d e l b a s i d ) w o l ( d e l b a n e 60 13 k l c i c p1 d e l b a s i d ) w o l ( d e l b a n e 59 2 k l c i c p1 d e l b a s i d ) w o l ( d e l b a n e 4- - 0 ) d e v r e s e r () d e v r e s e r ( 37 1 k l c i c p1 d e l b a s i d ) w o l ( d e l b a n e 26 0 k l c i c p1 d e l b a s i d ) w o l ( d e l b a n e 1- - 0 ) d e v r e s e r () d e v r e s e r ( 0- - 0 ) d e v r e s e r () d e v r e s e r ( byte 6: notes: 1 = enabled; 0 = disabled, outputs held low t i b# n i pe m a n n i pd w p n o i t p i r c s e d 0 = e u l a v t i b1 = e u l a v t i b 7- - 0 ) d e v r e s e r () d e v r e s e r ( 6- - 0 ) d e v r e s e r () d e v r e s e r ( 5- - 0 ) d e v r e s e r () d e v r e s e r ( 4- - 0 ) d e v r e s e r () d e v r e s e r ( 3- - 0 ) d e v r e s e r () d e v r e s e r ( 26 21 f e r1 ) d e l b a s i d ( ) w o l ( d e l b a n e 1- - 0 ) d e v r e s e r () d e v r e s e r ( 08 20 f e r1 ) d e l b a s i d ( ) w o l ( d e l b a n e serial bitmap t i bn o i t p i r c s e dd w p 7 % 5 5 2 . 0 d a e r p s r e t n e c : 0 % 6 . 0 - o t 0 d a e r p s n w o d : 1 0 4 : 6 t i b 4 5 6 u p ci c p 0 0 0 1 0 0 0 1 0 1 1 0 0 0 1 1 0 1 0 1 1 1 1 1 5 . 8 6 0 . 5 7 3 . 3 8 6 . 6 6 3 0 1 2 1 1 3 . 3 3 1 0 0 1 5 2 . 4 3 5 . 7 3 6 . 1 4 3 . 3 3 3 . 4 3 3 . 7 3 3 4 . 4 4 3 3 . 3 3 0 3 y b d e t c e l e s s i y c n e u q e r f - 0 # 6 . 6 6 / 0 0 1 l e s t c e l e s e r a w d r a h e v o b a 4 : 6 y b d e t c e l e s s i y c n e u q e r f - 1 0 2) d e v r e s e r ( 0 1 n o i t a r e p o l a m r o n - 0 0 e d o m t s e t - 1 0 n o m u r t c e r p s d a e r p s - 0 1 s t u p t u o l l a e t a t s i r t - 1 1 0 0
5 ICS9148-46 absolute maximum ratings supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = v ddl = 3.3 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd 0.1 5 m a input low current i il1 v in = 0 v; inputs with no pull-up resistors -5 2.0 m a input low current i il2 v in = 0 v; inputs with pull-up resistors -200 -100 m a operating i dd3 .3 op6 6 c l = 0 pf; select @ 66mhz 60 170 ma supply current i dd3.3op100 c l = 0 pf; select @ 100mhz 66 170 ma power down i dd3.3pd c l = 0 pf; with input address to vdd or gnd 3 650 m a supply current input frequency f i v dd = 3.3 v; 14.318 mhz c in logic inputs 5 pf c inx x1 & x2 pins 27 36 45 pf transition time 1 t trans to 1st crossing of target freq. 3 ms settling time 1 t s from 1st crossing to 1% target freq. 5 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target freq. 3 ms skew 1 t agp-pci1 v t = 1.5 v; 1 3.5 4 ns 1 guaranteed by design, not 100% tested in production. input capacitance 1 electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unles s otherwis e stated) parameter symbol conditions min typ max units operating i dd2.5op66 c l = 0 pf; select @ 66.8 mhz 16 72 ma supply current i dd2.5op100 c l = 0 pf; select @ 100 mhz 23 100 ma power down supply current i dd2.5pd c l = 0 pf; with input address to vdd or gnd 10 100 m a t cpu-agp 00.51 ns t cpu-pci2 v t = 1.5 v; v tl = 1.25 v 1 2.6 4 ns 1 guaranteed by design, not 100% tested in production. skew 1
6 ICS9148-46 electrical characteristics - cpuclk t a = 0 - 70c; v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh2 b i oh = -12.0 ma 2 2.3 v output low voltage v ol2 b i ol = 12 ma 0.2 0.4 v output high current i oh2 b v oh = 1.7 v -41 -19 ma output low current i ol2 b v ol = 0.7 v 19 37 ma rise time t r2b 1 v ol = 0.4 v, v oh = 2.0 v 1.25 1.6 ns fall time t f2b 1 v oh = 2.0 v, v ol = 0.4 v 1 1.6 ns duty cycle d t2b 1 v t = 1.25 v 454855% skew t sk2b 1 v t = 1.25 v 30 175 ps jitter, cycle-to-cycle t j c y c-c y c2b 1 v t = 1.25 v 150 250 ps jitter, one sigma t j 1s2b 1 v t = 1.25 v 40 150 ps jitter, absolute t jabs2b 1 v t = 1.25 v -250 140 +250 ps 1 guaranteed by design, not 100% tested in production. electrical characteristics - pciclk t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 30 pf parameter symbol conditions min typ max units output high voltage v oh1 i oh = -11 ma 2.4 3.1 v output low voltage v ol1 i ol = 9.4 ma 0.1 0.4 v output high current i oh1 v oh = 2.0 v -62 -22 ma output low current i ol1 v ol = 0.8 v 16 57 ma ris e time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 1.5 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 1.1 2 ns duty cycle 1 d t1 v t = 1.5 v 45 50 55 % skew 1 t sk1 v t = 1.5 v 140 500 ps jitter, one sigma 1 t j1s1 v t = 1.5 v 17 150 ps jitter, absolute 1 t jabs1 v t = 1.5 v -500 70 500 ps 1 guaranteed by design, not 100% tested in production.
7 ICS9148-46 electrical characteristics - ref t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -12 ma 2.6 3.1 v output low voltage v ol5 i ol = 9 ma 0.17 0.4 v output high current i oh5 v oh = 2.0 v -44 -22 ma output low current i ol5 v ol = 0.8 v 29 42 ma ris e time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 1.4 2 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 1.1 2 ns duty cycle 1 d t5 v t = 1.5 v 47 54 57 % jitter, one sigma 1 t j1s5 v t = 1.5 v 1 3 % jitter, absolute 1 t jabs5 v t = 1.5 v 3 5 % 1 guaranteed by design, not 100% tested in production. electrical characteristics - 48, 24 mhz t a = 0 - 70c; v dd = v ddl = 3.3 v +/-5%; c l = 20 pf (unless otherwise stated) parameter symbol conditions min typ max units output high voltage v oh5 i oh = -12 ma 2.6 3 v output low voltage v ol5 i ol = 9 ma 0.14 0.4 v output high current i oh5 v oh = 2.0 v -44 -22 ma output low current i ol5 v ol = 0.8 v 16 42 ma ris e time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 1.2 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 1.2 4 ns duty cycle 1 d t5 v t = 1.5 v 45 52 55 % jitter, one sigma 1 t j1s5 v t = 1.5 v 1 3 % jitter, absolute 1 t jabs5 v t = 1.5 v 3 5 % 1 guaranteed by design, not 100% tested in production.
8 ICS9148-46 general layout precautions: 1) use a ground plane on the top layer of the pcb in all areas not used by traces. 2) make all power traces and vias as wide as possible to lower inductance. notes: 1 all clock outputs should have series terminating resistor. not shown in all places to improve readibility of diagram 2 optional emi capacitor should be used on all cpu, sdram, and pci outputs. 3 optional crystal load capacitors are recommended. capacitor values: c1, c2 : crystal load values determined by user all unmarked capacitors are 0.01f ceramic
9 ICS9148-46 28 pin ssop package l o b m y s n o m m o c s n o i s n e m i d s n o i t a i r a v d . n i m. m o n. x a mn . n i m. m o n. x a m a8 6 0 . 03 7 0 . 08 7 0 . 04 19 3 2 . 04 4 2 . 09 4 2 . 0 1 a2 0 0 . 05 0 0 . 08 0 0 . 06 19 3 2 . 04 4 2 . 09 4 2 . 0 2 a6 6 0 . 08 6 0 . 00 7 0 . 00 28 7 2 . 04 8 2 . 09 8 2 . 0 b0 1 0 . 02 1 0 . 05 1 0 . 04 28 1 3 . 03 2 3 . 08 2 3 . 0 c4 0 0 . 06 0 0 . 08 0 0 . 08 27 9 3 . 02 0 4 . 07 0 4 . 0 ds n o i t a i r a v e e s0 37 9 3 . 02 0 4 . 07 0 4 . 0 e5 0 2 . 09 0 2 . 02 1 2 . 0 ec s b 6 5 2 0 . 0 h1 0 3 . 07 0 3 . 01 1 3 . 0 l5 2 0 . 00 3 0 . 07 3 0 . 0 ns n o i t a i r a v e e s 0 4 8 ics reserves the right to make changes in the device data identified in this publication without further notice. ics advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ordering information ics9148 y f-46 pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y f - ppp
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